1. Field of the Invention
The present invention relates to a data transfer circuit for transferring data between circuits that use clock signals having different cycles with respect to each other.
2. Description of the Related Art
FIGS. 2A and 2B of the accompanying drawings depict a conventional asynchronous data transfer method disclosed in Japanese Patent Kokai No. 2002-215568. FIG. 2A is a block diagram of an asynchronous interface circuit showing a TCLK (transmission side operation clock) operation section and a RCLK (reception side operation clock) operation section provided in an LSI. FIG. 2B is a signal waveform chart depicting an operation of the circuit shown in FIG. 2A.
As shown in FIG. 2A, the TCLK operation section includes a flip-flop (hereafter called ‘FF’) 1 for outputting a transfer reference signal STBT at a timing of a transmission side operation clock TCLK, and an FF 2 for loading transmission data DIT to be transmitted and for outputting it as transfer data DOT at the timing of the transmission side operation clock TCLK. The transfer reference signal STBT and the transfer data DOT are transferred to the RCLK operation section via transfer lines 3 and 4. The transfer lines 3 and 4 are laid out such that a delay of the transfer data DOT is more significant than that of the transfer reference signal STBT.
The RCLK operation section includes an FF 5 for loading a transfer reference signal STBR transferred via the transfer line 3 and for outputting it as a valid signal VAL at a timing of a reception side operation clock RCLK, and an FF 6 for loading transfer data DIR received from the transfer line 4 and for outputting output data DOR at the timing of the reception side operation clock RCLK.
In this asynchronous interface, the delay of the transfer data DOT is more significant than that of the transfer reference signal STBT, as described above, and a time difference between these delays is significant enough to always effectively sample the transfer data DIR at a clock edge by which an assertion of the transfer reference signal STBR is sampled first. Accordingly, as shown in FIG. 2B, the reception side can load the transfer data DIR sampled at an edge of the operation clock RCLK in the reception side by which an assertion of the transfer reference signal STBR is detected. The transfer data DIR can be used as output data DOR. The above mentioned Japanese Patent Kokai No. 2002-215568 teaches that, in spite of the asynchronous circuit, this circuit has a capability to make a simulation in a similar manner as a synchronous circuit and to verify the validity of the circuit.
The asynchronous interface in FIG. 2A, however, has the following problems. FIGS. 3A-3C of the accompanying drawings are charts depicting the problems of the conventional asynchronous interface.
(1) As shown in FIG. 3A, if a cycle of the reception side operation clock RCLK is longer than that of the transmission side operation clock TCLK, the transfer reference signal STBR cannot be loaded by means of the reception side operation clock RCLK when these clocks, i.e. TCLK and RCLK, are in a certain phase relationship. This may make it impossible to output the output data DOR to an FF in the next stage, even though the transfer data DIR shows a transition.
(2) As shown in FIG. 3B, if a cycle of the reception side operation clock RCLK is shorter than that of the transmission side operation clock TCLK, the valid signal VAL may be output before the transfer data DIR is verified, and thus uncertain output data DOR may be output to an FF in the next stage.
(3) As shown in FIG. 3C, if the transfer data DIR is slower than the transfer reference signal STBR, the output data DOR before update may be output or the output data DOR may become uncertain data, even though the valid signal VAL is active.
As described above, since the cycle of the transmission side operation clock TCLK is different from that of the reception side operation clock RCLK, the phase relationship of these clocks, i.e. TCLK and RCLK, is not fixed. Therefore it cannot be logically guaranteed that the transfer data DOT and the transfer reference signal STBT, which are driven by the transmission side operation clock TCLK, can be reliably loaded at the timing of the reception side operation clock RCLK.